1. Field of the Invention
The present invention relates to the preparation of substrates used in the manufacture of integrated circuits ("IC"), multichip modules, printed circuit boards, high-speed logic devices, flat panel displays, and other microelectronic devices. More particularly, the invention pertains to an improved technique for filling surface voids, leveling spaces between metal contacts and planarizing dielectric layers of substrates suitable for use in the manufacture of the above submicron size devices. This is done using spin-on glass materials together with a chemical mechanical polishing process.
2. Description of the Prior Art
A continuing trend in semiconductor technology is the formation of integrated circuit chips having more and faster circuits thereon. Such ultralarge scale integration has resulted in a continued shrinkage of feature sizes with the result that a large number of devices are available on a single chip. With a limited chip surface area, the interconnect density typically expands above the substrate in a multi-level arrangement and the devices have to be interconnected across these multiple levels. The interconnects must be electrically insulated from each other except where designed to make contact. Usually electrical insulation requires depositing or spinning-on dielectric films onto a surface. See, i.e., "Spin/Bake/Cure Procedure for Spin-On-Glass Materials for Interlevel and Intermetal Dielectric Planarization" brochure by AlliedSignal Inc. (1994)(thermally cured spun-on films).
A key processing difficulty associated with the formation of local interconnects is the topography of the device surface. Not only is the substrate surface itself quite non-planar, but device forming processes additionally create topographical irregularities such as gaps thereon. Loss of planarity can cause many problems which can adversely impact manufacturing yield including failure to open vias due to interlevel dielectric thickness disparity, poor adhesion to underlying materials, step coverage, as well as depth-of-focus problems. Thus the ability to fill narrow gaps in IC substrates is critical for forming sub-micron size elements thereon. Various substrate gap filling techniques known in the art include deposit-etch-deposit cycles, and applications of Sub-Atmospheric Tetra-Ethyl Ortho Silicate (SATEOS), Atmospheric Plasma Tetra-Ethyl Ortho Silicate (APTEOS), Chemical Vapor Deposition (CVD), High Density Plasma (HDP) systems and spin-on glass (SOG) materials. The technique employing the application of SOG materials is more economic than the other above equipment-intense techniques.
Other critical concerns in IC substrate processing include regional and global dielectric planarization. The planarization or smoothing of surfaces is essential in the fabrication of integrated circuits. As optical lithography techniques are used to define smaller and smaller features, the depth of focus of the exposure tool decreases. Therefore, it is necessary to employ planarizing films to smooth or "level" the topography of microelectronic devices in order to properly pattern the increasingly complex integrated circuits. IC features produced using photolithographic techniques require regional and global dielectric planarization where the lithographic depth of focus is extremely limited, i.e., at 0.35 .mu.m and below. Without sufficient regional and global planarization, the lack of depth of focus will manifest itself as a limited lithographic processing window.
One method for improving the planarization of IC surfaces includes chemical-mechanical polishing ("CMP"). Thus CMP has a unique advantage in that it can rapidly remove elevated topographical features without significantly thinning flat areas. CMP can reduce more of applied oxide coating thicknesses in raised areas than in recessed areas since the raised areas have a greater surface contact with the polishing pad and thus can be abraded to a greater extent than recessed areas. By applying mechanical as well as chemical abrasion to the upper surfaces, CMP achieves greater planarization than that obtained by conventional etching.
While planarization can be achieved with CMP, its use does not eliminate the need for gap-filling. It has been heretofore believed that the use of SOG and CMP techniques were mutually exclusive processes. This is because of the common belief that SOG layers are porous and hence the polish rate of SOG would be much higher than that of other gap-filling processes.
It would be desirable to provide an improved process for forming continuously uniform microelectronic substrates whereby the substrate would be essentially void-free, the metal contacts would be effectively insulated, and the layers would be effectively planarized.